The basic working principle of junction field effect transis

In the practical application of junction field effect transistor, the reverse bias applied to the gate junction is relative to the source, that is, the common source connection method is adopted, and the control power supply and the common end of the main power supply are connected in the same source. Due to the high conductivity of heavily doped gate materials, the potential of each point in the region is basically the same, that is, the gate is regarded as an equipotential region. However, this is not the case in the channel. Because the channel material is light doped, its resistivity is high. When there is current flowing between the drain and the source, there must be a potential gradient, that is, voltage drop. At this time, the bias voltage on the gate junction is no longer evenly distributed, and the width of the gate junction space charge region is no longer equal from the drain to the source. Figure 2 shows the three stages.

Fig. 2 conduction of Junction FET

1) Linear variation. When the current flowing through the junction field effect transistor is small, the potential gradient generated by the current in the channel is very small, which can be regarded as that the shape of the gate junction space charge region is affected very little, and the channel shape changes very little, as shown in Fig. 2A. In this case, it can be considered that the channel is a resistance region with fixed resistance value. The carrier drift motion in the channel satisfies Ohm's law, and the terminal voltage UDS changes linearly with the drain current ID.

2) Transition state. With the increase of drain current ID, the voltage drop in the channel increases, and the drain potential will be significantly higher than the source potential. Because the potential of the whole gate electrode is in reference to the source, the drain of the gate junction is in a reverse bias increasing state relative to the source. At this time, the space charge region of the gate junction gradually widens from the source to the drain, and the channel width correspondingly decreases, so the channel resistance increases, as shown in Fig. 2B. With the increase of UDS, this situation becomes more and more serious, and the deviation of ID from its linear value becomes larger and larger, which is called transitional state.

3) Saturation state. When the UDS voltage is higher than the transition region, the space charge regions on both sides of the channel will close from the drain end with the increase of UDS, and gradually advance the closing point to the source end slowly. The closure of the space charge region causes the conduction channel to be clamped off at the drain end. The essence of pinch off is that one end of the conductive channel becomes a space charge region where the carriers have been depleted, as shown in Fig. 2C. At this point, with the increase of UDS, Id no longer increases, which is called saturation state. It should be noted that there are essential differences between the higher UDS and the higher reverse bias UGS in the pinch off of conductive channels. The pinch off of higher reverse bias UGS is to make the whole conductive channel carrier exhausted, and the ID is zero; the pinch off of higher UDS only makes the drain end of the conductive channel partially depleted, and the electrons can still be swept through the space charge region and enter the drain by the strong electric field, so the ID is not zero, and the corresponding current is called saturation current.

4) Breakdown state. Once the drain end of the conductive channel becomes the space charge region, the rising of UDS will mainly fall in this high resistance region, where the electric field will become stronger and stronger, and the avalanche ionization effect of carrier multiplication in the space charge region will appear. As long as the UDS has a small increase, it will cause the sharp rise of ID, and eventually lead to device breakdown.